BEng (Hons) Electrical Electronic Engineering TM625: Electronics and Control Assignment 2 S13302 Table of Contents Table of Figures. 2 Abbreviations. 4 Task 1. 6 1. Explanation of a Weighted resistor DAC.

. 6 2. Explanation of a R-2R DAC.. 7 3. Explanation of a Successive Approximation ADC.. 8 Task 2.

9 1. Explain circuit operation and modes. 9 2. Acquisition time. 10 3. Aperture time.

10 4. Drift Rate. 11 5. Settling time. 11 6. Hold step.

12 7. Turn – off time. 12 8. Time taken for the Capacitor voltage to reach 99% of the input.

13 Task 3. 14 1. TF = (2S+9)/(S2+2S+4), Gain of 2. 14 2. PID System..

17 3. PI System..

20 4. PD System.. 23 5. Compare Transfer Function with Second order system equation.. 26 6.

Comparison of the performance of PI, PD and PID systems. 27 Task 4. 28 1. Flash ADC.. 28 2. Circuit Build Figures. 29 References.

32 Table of Figures Figure 1: Weighted Resistor DAC Circuit (Wilkins et al., 1975) 6 Figure 2: R-2R Ladder DAC Circuit 7 Figure 3: Successive Approximation ADC (Kester, 2008) 8 Figure 4: Sample and hold circuit 9 Figure 5: Acquisition time graph (Kester, 2009) 10 Figure 6: Aperture Time Graph (Kester, 2009) 10 Figure 7: Drift Rate Graph (Kester, 2009) 11 Figure 8: Settling Time Graph (Instruments, 1992) 11 Figure 9: Hold Step Graph (Instruments, 1992) 12 Figure 10: Turn Off Time (Kester, 2009) 12 Figure 11: RC Time Constant Table (Patrick and Fardo, 2000) 13 Figure 12: Transfer Function System.. 14 Figure 13: PID System Response.

14 Figure 14: PID Steady State Error 15 Figure 15: PID Values. 16 Figure 16: PID System..

17 Figure 17: PID Response. 17 Figure 19: PID Steady State Error 18 Figure 18: PID Gain.. 18 Figure 20: PID Derivative. 19 Figure 21: PID Intergrator 19 Figure 22: PI System..

20 Figure 23: PI System Response. 20 Figure 24: PI Steady State Error 21 Figure 25: PI Integrator 21 Figure 26: PI Gain.. 22 Figure 27: PI Derivative. 22 Figure 28: PD System.. 23 Figure 29: PD System Response. 23 Figure 30: PD Steady State Error 24 Figure 31: PD Integrator 24 Figure 32: PD Gain.

. 25 Figure 33: PD Derivative. 25 Figure 34: System Damping. 26 Figure 35: Flash ADC Schematic. 28 Figure 36: Priority Encoder Function Table (Instruments, 2004) 28 Figure 37: Flash ADC Circuit Build.

29 Figure 38: Flash ADC Circuit Build. 29 Figure 39: Flash ADC LEDs. 30 Figure 40: Flash ADC Circuit 30 Abbreviations DAC Digital to Analogue Converter ADC Analogue to Digital Converter MSB Most significant bit LSB Least significant bit SAR Successive Approximation Register FET Field-effect transistor PID Proportional–Integral–Derivative Controller Task 1 1. Explanation of a Weighted resistor DAC V1 V2 V3 V4 Figure 1: Weighted Resistor DAC Circuit (Wilkins et al., 1975) The weighted resistors DAC circuit consists of resistors and an operational amplifier. Vout is sum of the input voltages. If the values of the input resistors are set to multiples of two e.

g. 1kohm, 2kohm, 4kohm, 8kohm, the output voltage would be equal to the sum of the input voltages multiplied by the ratio of input resistors and feedback resistor, this gives the equation: (Wilkins et al., 1975) Therefore if, VR = 5V, V1 = 1, V2 = 0, V3 = 1, V4 = 1 or 1011 and Rf = 1,000 Ohms. The output formula would be: k = -0.6875V 2. Explanation of a R-2R DAC The circuit for a 4-bit DAC using binary weighted resistor network is shown below: Figure 2: R-2R Ladder DAC Circuit An alternative to the Weighted Resistor DAC is the R-2R Ladder DAC. This type of DAC uses two resistor values, R and 2 * R. when each input is supplied with a logic level 0 or a logic level 1 the output will be the voltage equivalent and the binary input.

It’s advantage of the weighted resistor DAC is that it has fewer different values. The output can be given from the equation: (Electronics, 2004) Where: · Rf = R9 (20,000Ohms) · Ra = R7 (10,000Ohms) · N = number in decimal form i.e. 1001 = 9. · n = number of bits in the system i.

e. 4 bits in total. · Vr = reference voltage, i.e. 5V Therefore, to calculate the output if the binary input is 1001 would be; 3. Explanation of a Successive Approximation ADC Figure 3: Successive Approximation ADC (Kester, 2008) The Successive Approximation ADC is a convertor that continuously converts an analogue signal into a digital output by a binary search method. The SAR ADC start by trying all the values of bits starting the MSB and finishing with the LSB. For example, a SAR ADC with 4-bit resolution.

· Vref = 1V · Vin = 0.6V. · Vadc = internal comparator voltage The ADC starts with the MSB (Bit-3). Vref is divided by 2 and compared with Vin. As Vin is greater than Vref/2, it turns MSB to a logic 1. 1 X X X The next calculation is for the MSB-1 (bit-2), Vin is compared to Vadc = Vref/2+Vref/4 = 0.5+0.

25V = 0.75. As Vin < Vadc (0.75V) bit 2 is turned off. 1 0 X X For MSB-2 (bit-1) is compared with Vref/2 + Vref/8 = 0.625. as 0.

6V < 0.625, the MSB is turned off. 1 0 0 X For MSB-3 (bit-0) is compared with Vref/2 + Vref/16 = 0.5625. as 0.6V > 0.5625, the MSB is turned on.

1 0 0 1 Task 2 Figure 4: Sample and hold circuit 1. Explain circuit operation and modes The sample and hold circuit is used to capture an analogue voltage. There are two modes – sample (also known as track) and hold, below is a description of the operation of each. In the sample mode, the sample control node is held to a logic 1 – the buffered input voltage flows the FET and charges the capacitor.

In this mode the output voltage will match the input voltage. In the hold mode, when the sample control node is a logic 0, the FET is turned off. At this point the capacitor is disconnected from the input circuitry and retains the sampled voltage, this is then slowly discharged through the resistor and the op-amp to create a Vout. 2.

Acquisition time Figure 5: Acquisition time graph (Kester, 2009) The acquisition time is the length of time that the circuit must remain in the sample mode to acquire a full-scale output. The maximum acquisition time arises when the hold capacitor charges to a full-scale voltage change. This period depends on the size of the hold capacitor. The acquisition time can be reduced by choosing a smaller value capacitor, however this will also increase discharge rate. 3.

Aperture time Figure 6: Aperture Time Graph (Kester, 2009) The aperture time, is the delay between the hold signal being applied and the input signal being disconnected from the hold capacitor. 4. Drift Rate Figure 7: Drift Rate Graph (Kester, 2009) This drift rate can be expressed in V/us, during the hold mode there can be errors in the holding capacitor, the buffer amplifiers and switch. If a leakage current flows in or out of the hold capacitor, this would slowly reduce or increase the voltage in the capacitor. 5. Settling time Figure 8: Settling Time Graph (Instruments, 1992) The settling time is the time that the system takes for the output voltage to stabilise within an error band after the system has received the hold command. 6. Hold step Figure 9: Hold Step Graph (Instruments, 1992) The hold step is the voltage at the output due to the sample-to-hold transition.

It is caused by a transfer of charge to the hold capacitor due to the opening of the switch. 7. Turn – off time Figure 10: Turn Off Time (Kester, 2009) The turn off time is the delay time between the hold command being sent to the switch and the point when the final voltage charge is held at the capacitor. 8. Time taken for the Capacitor voltage to reach 99% of the input. · ON resistance = 30? · C1 = 1µF Time Constant RC Value Voltage percentage of max.

1.0 time constant 1T = 1RC 63% 2.0-time constants 2T = 2RC 86% 3.0-time constants 3T = 3RC 95% 4.0-time constants 4T = 4RC 98% 5.

0-time constants 5T = 5RC 99% Figure 11: RC Time Constant Table (Patrick and Fardo, 2000) The formula to calculate the time the voltage in the capacitor charges to within 1 percent of the input voltage is: (Patrick and Fardo, 2000) Therefore, Task 3 1. TF = (2S+9)/(S2+2S+4), Gain of 2 Figure 12: Transfer Function System Figure 13: PID System Response The graph above shows the system response, settling at around 7 seconds. Figure 14: PID Steady State Error The graph above shows a steady state error of 0.0001 Figure 15: PID Values P = 0.2222222222, I = 0.00000000001 D = 0.00000000001 2. PID System Figure 16: PID System Figure 17: PID Response The above graph is the response of the PID system, shown to settle at around 8 seconds.

Figure 19: PID Steady State Error The above graph is the steady state error of the PID system, with an error of 0.0001. Figure 18: PID Gain G = 0.1 Figure 20: PID Derivative D = 50 Figure 21: PID Intergrator I = 0.1749 3. PI System Figure 22: PI System Figure 23: PI System Response The graph above is the response of the PI system, shown to settle at around 8 seconds. Figure 24: PI Steady State Error The graph above is the steady state error of the PID system, with an error of 0.0 Figure 25: PI Integrator I = 0.

1749 Figure 26: PI Gain G = 0.1 Figure 27: PI Derivative D = 0 4. PD System Figure 28: PD System Figure 29: PD System Response The graph above is the response of the PD system, shown to settle at around 9 seconds. Figure 30: PD Steady State Error The graph above is the steady state error of the PID system, with an error of 0.0008 Figure 31: PD Integrator I = 0 Figure 32: PD Gain G = 0.165 Figure 33: PD Derivative D = 50 5. Compare Transfer Function with Second order system equation The second order transfer function can be expressed as: (Levine, 2011) The damping ratio, is a value signifying the amount at which an oscillation in the systems response reduces due to effects, such as resistance. If; >1 the system is over-damped <1 the system is under-damped =1 the system is critically-damped Figure 34: System Damping refers to the natural frequency that the system will oscillate (in rad/s) when =0.

K refers to the DC gain of the system, this is the ratio of the magnitude of the steady-state response to the input. 6. Comparison of the performance of PI, PD and PID systems In the PID system the overshoot reaches just under 0.2, the PI system has a similar overshoot while the PD system reaches 0.35. All the systems reach a steady state at around 8 seconds.

The steady state error of the PD system is the largest at 0.0008, the PI error is 0.0 and the PID steady state error is 0.0001. To reduce the steady state error, the rise time and the stability of the system there were three variables; Kp – this is the proportional controller which had the effect of reducing the rise time Ki – this is the integral controller which had the effect of reducing the steady state error.

Kd – this is the derivative controller which has the effect of reducing the over shoot. From the results of the PID, PD and PI simulations the PI controller can be used to reduce the steady state error, the PD controller is the most unstable system with the largest overshoot. The PID has a very low steady state error and rises the fastest. Task 41. Flash ADC Figure 35: Flash ADC Schematic(Ashby, 2008)A flash ADC consists of an array ofcomparators, a resistor voltage divider and an encoder. The divider network issupplied with a reference voltage. Therefore, each comparator compares an attenuatedreference voltage with the analogue input voltage. The priority encoder takesthe 8 inputs and reduces them into a binary output see figure 35.

The flash ADCis suggested to be most efficient type of ADC, being limited only by the propagationdelay of the gates. The disadvantage of this ADC is that it requires anextensive number of components. Figure 36: PriorityEncoder Function Table (Instruments, 2004) 2. Circuit Build Figures Figure37: Flash ADC Circuit Build Figure 38: Flash ADC Circuit Build Figure 39: Flash ADCLEDs Figure 40: Flash ADC Circuit Part of this assignment was to construct aFlash ADC using the circuit in figure 37;· 1x LM74148- priority encoder · 2x LM339– Quad differential amplifier· 18x1k resistors· 7x3k resistors· 10xLEDs· 1x100ohm potentiometerDuringthe circuit build the author attempted to test the circuit in modular blocks toensure that was built so far was functioning as intended. Initially the circuitwas built without the priority encoder the connected, once tested only threeLEDs were illuminating, the other five LEDs were not working, possible due anincorrect wire somewhere in the circuit. References· Kester,W. (2009). Aperture Time, Aperture Jitter, Aperture Delay Time— Removingthe Confusion.

1st ed. ebook ANALOG DEVICES. Available at:http://www.analog.com/media/en/training-seminars/tutorials/MT-007.pdf Accessed18 Jan. 2018.· Instruments,T.

(1992). Specifications and Architectures of Sample-and-Hold Amplifiers. 1sted.

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cn/cn/lit/an/snoa223/snoa223.pdf Accessed 18 Jan. 2018.· Electronics,T. (2004). R/2R LADDER NETWORKS – Application Note. 2nd ed.

ebook TTElectronics. Available at:http://www.ttelectronics.com/themes/ttelectronics/datasheets/resistors/literature/LADDERNETWORKS.pdfAccessed 19 Jan. 2018.· Grout,I.

(2006). Integrated Circuit Test Engineering. New York: Springer-VerlagLondon Limited.

· Patrick,D. and Fardo, S. (2000). Understanding DC circuits. Boston: Newnes.· Levine,W.

(2011). Control system fundamentals. Boca Raton, Fla. u.a.

: CRC Press.· Instruments,T. (2004). 8-Line to 3-Line Priority Encoders. ebook TI. Available at:http://www.ti.com/lit/ds/symlink/sn74ls148.

pdf Accessed 19 Jan. 2018.· Kester, W. (2008). ADC Architectures II: SuccessiveApproximation ADCs. 1st ed. ebook ANALOG DEVICES.

Available at:http://www.analog.com/media/en/training-seminars/tutorials/MT-021.pdf Accessed19 Jan. 2018.· DACAND BINARY-WEIGHTED RESISTOR DAC.

(2014). 1st ed. ebook IDC Online.

Availableat:http://www.idc-online.com/technical_references/pdfs/electronic_engineering/Dac_And_Binary_Weighted_Resistor_Dac.pdfAccessed 19 Jan. 2018.

· Wilkins,C., Perone, S., Klopfenstein, C., Williams, R. and Jones, D. (1975). DigitalElectronics and Laboratory Computer Experiments.

Boston, MA: Springer US.· Ashby,D. (2008). Circuit design.

Amsterdam etc.: Newnes/Elsevier.