Dulari total harmonic distortion. h an input signal

DulariTandon, International Institute of Information Technology, Naya Raipur, Email:[email protected],International Institute of Information Technology, Naya Raipur,Email:[email protected]

inAbstract: The concept of this paper is a dynamicamplifier topology for analog-to-digital -converters. In this method an inputsignal of 100 mVpp,  diff and 4× gain isprovided  to achieve  100-dB total harmonic distortion. h an input signal of 100 m Vpp ,  diff and 4× gain, it achieves ?100-dB totalharmonic distortion, the lowest ever reported for a dynamic amplifier.  This method has an improved linearity of 25dB having twice the output swing. The improvement in linearity is accomplishedwith a new linearization technique based on capacitive degeneration, whichexploits the exponential voltage-to-current relationship of MOSFET in weakinversion.

The proposed  amplifier inthis paper is fabricated in a 28-nm CMOS process.Keywords: Amplifier, analoglinearization technique, analog-to-digital converter (ADC), capacitivedegeneration, digital nonlinearity calibration, integrator.I.                   INTRODUCTIONThe demand foranalog-to-digital converters (ADC) having more bandwidth and lower powerconsumption has been increased with the advancement of software defined radio(SDR) technology. The demand for Software Defined Radio (SDR) technique  is increased because of its flexibility, costefficient having lot of advantages. Butin other  wireless communication systemssuch as GSM or LTE, a weak signal is required  to be processed using blocker. So the widebandanalog-to-digital converter (ADC) is not sufficient for this system, becausethe channel selection is done in the digital domain, not in the analogfront-end.

Due to these blockers strict linearity is required(>80 dB) on theanalog-to-digital converters (ADC) 2, so the analog-to-digital converters (ADC)nonlinearity cannot be improved just by digital filtering and it needs to bepower efficient 3.Pipelined  analog-to-digital converts (ADCs) are chosenfor wide-bandwidth and moderate-to-high resolution (>10 b) applications. Ina pipelined analog-to-digital converters  (ADC), amplifiers are used to improve thenoise performance. For this they must have sufficiently low noise andnonlinearity to enhance analog-to-digital converters’ performance. Since noiseis basic factor which exists in practical, to get  the desired noise level it requires a certainamount of power consumption. Nonlinearity causes deterministic errors and it canbe improved by analog 4 or digital 5 techniques. The main objective  is to improve linearity with minimum possiblepower consumption.

Best services for writing your paper according to Trustpilot

Premium Partner
From $18.00 per page
4,8 / 5
4,80
Writers Experience
4,80
Delivery
4,90
Support
4,70
Price
Recommended Service
From $13.90 per page
4,6 / 5
4,70
Writers Experience
4,70
Delivery
4,60
Support
4,60
Price
From $20.00 per page
4,5 / 5
4,80
Writers Experience
4,50
Delivery
4,40
Support
4,10
Price
* All Partners were chosen among 50+ writing services by our Customer Satisfaction Team

Residue amplificationwith high linearity (>60 dB) traditionally depends upon closed-loopamplifiers with high loop gain. However, these require large bandwidth,reducing the power efficiency. Alternative amplifier techniques has beenintroduced to improve the amplification efficiency. Dynamic amplifiers (orintegrators)  allow for the lowestpossible small-signal bandwidth and hence the lowest power consumption. However,they demonstrate more nonlinearity. Digital nonlinearity standardisation can beused for the error detection and correction.

Although error detection andcorrection can be done at a lower rate compared to the sampling speed (FS),digital error correction needs logic operating at FS, and also consumes relativepower.In this paper, a newlinearization technique is proposed that presents capacitive degeneration toconsiderably improve the linearity of a integrator (dynamic amplifier). Itemploys a cross-coupled capacitor configuration reduces capacitor size andimproves common-mode (CM) rejection capability. For compensation, theamplifier can be placed in a slow control loop which digitally detects anyresidual nonlinearity and minimizes it through an analog control-voltage with consumingnegligible power. II.                 CAPACITIVELYDEGENERATED LINEARIZATION TECHNIQUE The introduced linearization techniqueassuming that the MOSFETs are biased in the weak inversion saturation region,where their voltage-to-current (V–I) relationship is exponential.

The sameconcept can therefore be applied to bipolar junction transistors as well, sincetheir V –I characteristic is also exponential. In this section, the CDLtechnique is first explained intuitively, and then analytically. Finally, theeffect of this technique on the amplifier’s overall noise performance isdiscussed.