James 2.4.1 Operation The function of the CBG

James W.
Tschanz,Siva G. Narendra, MeYibin
Ye,  Bradley A. Bloechel,
ShekharBorkarand Vivek De 6 proposedin
order to manage the active power consumption of high-performance digital
designs. Active leakage control techniques are needed to provide significant
leakage power savings coupled with fast time constants for entering and exiting
idle mode. In this paper, dynamic sleep transistors and body bias are used in
conjunction with clock gating to control active leakage for a 32-bit integer
execution core in 130-nm CMOS technology. Measurements onpMOSsleep transistor
reveal that lowest-leakage state is reached in less than 1 ms, resulting in 37×
reduction in leakage power, while reactivation of block is achieved in less
than two clock cycles. Power measurements at 4 GHz, 1.3 V, 75 C demonstrate 8%
total power reduction using dynamic body bias and 15% power reduction using a
pMOS sleep transistor, for a typical activity profile.

test chip also contains the components required for applying dynamic body bias
to pMOS transistor in the adder core. When the core is in active mode, FBB is
applied to reduce the Vt of the devices, increasing the performance.

measurements of testchip  have shown
that, at high temperature, thefrequency is maximized by the application of
450mVFBB.When the core is idle, zero body bias (ZBB) or RBB may be applied and
hence leads to  increase inVt and
reducing the leakage. The bodybias circuitry consists of two main blocks: a
central bias generator(CBG) and many distributed local bias generators (LBGs)
(Fig 2.7).


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                  The function of the CBG is to
generate a process of voltage, and temperature-invariant reference voltage
which is then routed to the LBGs.The CBG uses a scaled bandgap circuitto
generate a reference voltage which is 450 mV belowthe bandgap supply Vcca—this
represents the amount of forward bias needed to apply in
active mode. This reference voltage is then routed to all the distributed LBGs,
shielded on both sides byVcca. The function of the LBG is to translate this
voltage, referenced toVcca, a body voltage which is referenced to the local
block Vcc. This ensures that any variations in the localVccwill be tracked by
the body voltage, maintaining a constant450 mV of FBB. Translation of the
reference can be done  through the use of
a current mirror followed by a voltage buffer to drive the final nwell load.
Low-frequency tracking of such supply variations can be handled by the current
mirror while a capacitorprovides the high-frequency tracking. In idle mode, the
currentmirror is disabled and a zero-bias switch transistor connects thebody to
Vcc, while applying ZBB for leakage reduction. While RBBmay be applied during
idle mode for further leakage power savings,studies show that the effectiveness
of RBB is diminishing with technology scaling and, therefore, we cannot  justify theadditional complexity required.