James W.Tschanz,Siva G. Narendra, MeYibinYe, Bradley A. Bloechel,ShekharBorkarand Vivek De 6 proposedinorder to manage the active power consumption of high-performance digitaldesigns. Active leakage control techniques are needed to provide significantleakage power savings coupled with fast time constants for entering and exitingidle mode. In this paper, dynamic sleep transistors and body bias are used inconjunction with clock gating to control active leakage for a 32-bit integerexecution core in 130-nm CMOS technology. Measurements onpMOSsleep transistorreveal that lowest-leakage state is reached in less than 1 ms, resulting in 37×reduction in leakage power, while reactivation of block is achieved in lessthan two clock cycles.
Power measurements at 4 GHz, 1.3 V, 75 C demonstrate 8%total power reduction using dynamic body bias and 15% power reduction using apMOS sleep transistor, for a typical activity profile. Thetest chip also contains the components required for applying dynamic body biasto pMOS transistor in the adder core. When the core is in active mode, FBB isapplied to reduce the Vt of the devices, increasing the performance.Previousmeasurements of testchip have shownthat, at high temperature, thefrequency is maximized by the application of450mVFBB.When the core is idle, zero body bias (ZBB) or RBB may be applied andhence leads to increase inVt andreducing the leakage. The bodybias circuitry consists of two main blocks: acentral bias generator(CBG) and many distributed local bias generators (LBGs)(Fig 2.
7).2.4.1Operation The function of the CBG is togenerate a process of voltage, and temperature-invariant reference voltagewhich is then routed to the LBGs.
The CBG uses a scaled bandgap circuittogenerate a reference voltage which is 450 mV belowthe bandgap supply Vcca—thisrepresents the amount of forward bias needed to apply inactive mode. This reference voltage is then routed to all the distributed LBGs,shielded on both sides byVcca. The function of the LBG is to translate thisvoltage, referenced toVcca, a body voltage which is referenced to the localblock Vcc. This ensures that any variations in the localVccwill be tracked bythe body voltage, maintaining a constant450 mV of FBB. Translation of thereference can be done through the use ofa current mirror followed by a voltage buffer to drive the final nwell load.Low-frequency tracking of such supply variations can be handled by the currentmirror while a capacitorprovides the high-frequency tracking.
In idle mode, thecurrentmirror is disabled and a zero-bias switch transistor connects thebody toVcc, while applying ZBB for leakage reduction. While RBBmay be applied duringidle mode for further leakage power savings,studies show that the effectivenessof RBB is diminishing with technology scaling and, therefore, we cannot justify theadditional complexity required.